This invention relates to the field of semiconductor processing. More particularly the invention relates to a conduction layer that is treated to resist erosion and undesirable interaction with other layers.
In general concept, integrated circuits are typically formed as a multitude of individual devices that are electrically connected one to another. The devices are often formed in a material, such as a semiconductor material, and the electrical connections that provide communication between the active devices are typically formed of another material, such as a metal or a series of metals, or a different phase of the semiconductor material, such as doped polysilicon.
In the example of the conduction layer that is formed of a series of metals, each of the individual metal layers in the conduction layer stack is typically selected to provide a specific function for the conduction stack as a whole. For example, a first deposited layer of the conduction stack may be selected for its ability to adhere tightly to the underlying material. As a specific example of a metal that performs this function, titanium can be used as an adhesion layer on top of silicon, as it adheres very tightly to both the silicon and the silicon oxide that may be beneath it, and tends to prevent the conduction stack from peeling off of the underlying silicon and silicon dioxide.
A second metallic layer may be used to prevent interaction between any of layers below it with any of the layers above it. Titanium nitride may be used to prevent reactions between a titanium adhesion layer and an aluminum layer, or between an aluminum layer and an underlying silicon substrate. An aluminum layer may be used as a primary conduction layer for the communication of electrical charges. Finally, the primary conduction layer may be overlaid with an optical antireflection layer, so that the entire conduction stack can be more easily patterned using photolithographic techniques.
After all of these layers have been sequentially deposited, the conduction stack is patterned with the specific geometry that is desired for the layer. This is most typically accomplished by coating the conduction stack with a layer of photoresist, exposing the photoresist to a mask pattern, developing the photoresist to remove the photoresist from those areas where the conduction stack is also to be removed, and then etching away those portions of the conduction stack that are exposed. The etching may be accomplished by means of either a physical etch, such as by ion bombardment, or a chemical etch, such as in an acid solution. These two types of etching can be combined such as in a reactive ion etch, which combines elements of both a physical and a chemical etch.
After the conduction stack has been patterned, it is typically covered with an insulating layer of a material that has a high dielectric coefficient, such as silicon oxide. Holes are then etched through the dielectric layer to make contact to the underlying conduction stack. The contact holes are called vias. The topmost layer of the underlying conduction stack often has another function that is used during the formation of the vias. The topmost layer may be selected so as to provide a positive stop to the etching process used to form the vias. Thus, the etchant method as described above etches completely through the dielectric layer, but does not etch appreciably into the conduction stack. In other words, the topmost layer of the conduction stack is selected so to not be appreciably attacked by the etchant that is used to etch the vias. In this manner, the vias are completely etched out, but the conduction stack is not attacked or diminished either physically or chemically by the etchant.
After the vias to the underlying conduction stack are etched, a top conduction layer is deposited, which top layer makes electrical contact to the underlying conduction stack through the vias. At this point, yet another function of the topmost layer of the conduction stack is utilized. The topmost layer of the conduction stack is selected so as to not react with the material of the top conduction layer, and additionally may act as a barrier between the material of the top conduction layer and the underlying layers of the conduction stack. Therefore, it is often preferred that the vias completely overly only contiguous upper surfaces of the underlying conduction stack.
Unfortunately, as the geometries of integrated circuits decrease, it becomes increasingly harder to align the via openings to a contiguous upper surface of the underlying conduction stack. Often, a portion of the via opening contacts the underlying conduction stack at the patterned edge of the conduction stack. Thus, a first portion of the via overlies the upper surface of the conduction stack, and another portion of the via overlies the sidewall of the patterned edge of the conduction stack. While such a misalignment may still provide an overlap between the underlying conduction layer and the top conduction layer that is sufficient for electrical conductivity and adequate current flow, there are other problems that are brought about by the misalignment. For example, if the material of the topmost layer of the conduction stack is preferentially selected to provide an etch stop during the via etch, then this function is not provided to those edges of the underlying layers of the conduction stack that are exposed by the misaligned via that partially overlaps the edge of the patterned conduction stack.
Further, and in a similar vein, if the material of the topmost layer of the conduction stack is preferentially selected to provide a barrier between the top conduction layer and the underlying layers of the lower conduction stack, then this function is also not provided to those edges of the underlying layers of the conduction stack that are exposed by the misaligned via that partially overlaps the edge of the patterned conduction stack.
What is needed, therefore, is a process to produce a conduction stack that tolerates the problems associated with misalignment of the vias without the loss of the functionality that typically accompanies such misalignment.
The above and other needs are met by an interconnection system having a bottom metal layer that has a conduction layer with a sidewall and an overlying barrier layer. A lateral barrier layer is disposed adjacent the sidewall of the conduction layer, and an insulation layer is over the bottom metal layer. The insulation layer forms vias extending through the insulation layer to the bottom metal layer. A top metal layer extends through the vias to electrically contact the bottom metal layer. The overlying barrier layer and the lateral barrier layer are relatively resistant to interaction with the top metal layer as compared to the conduction layer.
Thus, the interconnection system described above solves the problems recited above by providing a lateral barrier layer that protects the conduction layer of the bottom metal layer. The lateral barrier layer is relatively resistant to interaction with the top metal layer, as compared to the conduction layer. This is significant for those occasions when the vias are misaligned to the bottom metal layer and at least partially overlie the patterned sidewall of the bottom metal layer. In a typical bottom metal layer stack, this situation presents an exposed sidewall surface of the conduction metal layer. However, in the structure described above, the top metal layer does not degrade the function or integrity of the conduction layer in any way, because the lateral barrier keeps the top metal layer and the conduction layer from contacting one another. Further, the lateral barrier layer reduces erosion of the conduction layer during the via etch process.
In various preferred embodiments, the conduction layer is aluminum and the overlying barrier layer is titanium nitride. The lateral barrier layer is preferably aluminum oxide. In a most preferred embodiment the bottom metal layer has an adhesion layer of titanium, an underlying barrier layer of titanium nitride, a conduction layer of aluminum, and an overlying barrier layer of titanium nitride.
In a method for producing an interconnection system according to the present invention, a bottom metal layer is deposited by depositing a conduction layer and forming an overlying barrier layer. The bottom metal layer is patterned to produce a patterned bottom metal layer having a sidewall. A lateral barrier layer is formed against the sidewall of the bottom metal layer, and an insulation layer is deposited over the bottom metal layer. Vias are etched through the insulation layer to the bottom metal layer using an etchant. The overlying barrier layer and the lateral barrier layer are relatively resistant to the etchant as compared to the insulation layer. A top metal layer is deposited through the vias to electrically contact the bottom metal layer. The overlying barrier layer and the lateral barrier layer are relatively resistant to interaction with the top metal layer as compared to the conduction layer.
Thus, this method produces a bottom metal layer where at least the sidewall of the conduction layer is protected by the lateral barrier layer. Therefore, when the vias are misaligned and the sidewall of the patterned bottom metal layer is exposed in the via, the sidewall of the conduction layer will not contact the overlying top metal layer. Further, the etchant used to create the via will similarly not contact the sidewall of the conduction layer.
Various different preferred methods may be used to form the lateral barrier layer. For example, the lateral barrier layer can be formed against the sidewall of the bottom metal layer by interacting the sidewall of the bottom metal layer with one or more of a liquid chemical, a gas, or a plasma. The lateral barrier layer may be formed adjacent the entire sidewall of all of the different layers of the bottom metal layer, or adjacent just the sidewall of the conduction layer of the bottom metal layer. Further, the lateral barrier layer may be formed by deposition, such as by a chemical reaction or a plasma deposition.